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Integrated Circuit Systems, Inc.
ICS91309
High Performance Communication Buffer
General Description
The ICS91309 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz. The ICS91309 provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. ICS91309 has two banks of four outputs controlled by two address lines. Depending on the selected address line, bank B or both banks can be put in a tri-state mode. In this mode, the PLL is still running and only the output buffers are put in a high impedance mode. The test mode shuts off the PLL and connects the input directly to the output buffers (see table below for functionality). ICS91309 comes in a 16-pin 150 mil SOIC, SSOP or 4.40mm TSSOP package. In the absence of REF input, the device will enter a powerdown mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition.
Features
* * * * * * * * * * Zero input - output delay Frequency range 10 - 133 MHz (3.3V) 5V tolerant input REF High loop filter bandwidth ideal for Spread Spectrum applications. Less than 125 ps cycle to cycle Jitter Skew controlled outputs Available in 16 pin, 150 mil SSOP, SOIC & 4.40mm TSSOP packages Skew: Group-to-Group: <215 ps Skew within Group: <100 ps Commercial temperature range: 0C to +70C
Pin Configuration
REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 FS2 1 2 16 15 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 FS1
4 5 6 7 8
ICS91309
3
14 13 12 11 10 9
Block Diagram
16 pin SSOP, SOIC & TSSOP
Functionality
FS2 FS1 CLKA(1:4) CLKB(1:4) CLKOUT 0 0 1 1 0 1 0 1 Tristate Driven PLL Bypass Mode Driven Tristate Tristate PLL Bypass Mode Driven Driven Driven PLL Bypass Mode Driven Ouput PLL Source Shutdown PLL N PLL N REF PLL Y N
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ICS91309
Pin Descriptions
PIN # PIN NAME 1 REF1 2 CLKA12 3 CLKA22 4, 13 VDD 5, 12 GND 6 CLKB12 7 CLKB22 8 FS23 9 FS13 10 CLKB32 11 CLKB42 14 CLKA32 15 CLKA42 16 CLKOUT2 Notes: 1. Weak pull-down 2. Weak pull-down on all outputs 3. Weak pull-ups on these inputs PIN TYPE IN OUT OUT PWR PWR OUT OUT IN IN OUT OUT OUT OUT OUT DESCRIPTION Input reference frequency, 5V tolerant input Buffered clock output, Bank A Buffered clock output, Bank A Power Supply Ground Buffered clock output, Bank B Buffered clock output, Bank B Function select input, bit 2 Function select input, bit 1 Buffered clock output, Bank B Buffered clock output, Bank B Buffered clock output, Bank A Buffered clock output, Bank A Buffered clock output, internal feedback
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ICS91309
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs (Except REF) . . . . . . . . . . . . . . GND -0.5 V to VDD + 0.5 V Logic Input REF . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to GND + 5.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-10% PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD IIL VIN = 0 V Input Low Current Output High Voltage VoH IoH = -12 mA Output Low Voltage VoL IoL = 12 mA Operating Supply IDD Outputs Unloaded; REF = 66 MHz Current Powerdown Current Input Frequency Input Capacitance
1
MIN 2
TYP
MAX 0.8 100 50 0.4
0.1 19 2.4
UNITS V V uA uA V V mA uA MHz pF
30 0.3 10
45 12 133 5
IDD Fi CIN
REF = 0 Mhz
NOTES: 1. Guaranteed by design and characterization, not 100% tested in production.
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ICS91309
Electrical Characteristics - Outputs
TA = 0 - 70C; VDD = 3.3 V +/-10%; CL = 30 pF (unless otherwise specified) PARAMETER Output High Voltage Output Low Voltage Rise Time 1 Fall Time PLL Lock Time1 Output Frequency Duty Cycle
1 1 1
Jitter, Cycle-to-cycle Jitter, Absolute1 Jitter, 1-Sigma1 1 Skew, Group-to-Group Skew, Output-to-Output1 Skew, Device-to-Device1 Delay, Input-to-Output1
SYMBOL VOH VOL tr tf TLOCK f1 f1 Dt1 Dt2 tjcyc-cyc Tjabs Tj1s Tsk Tsk Tdsk-Tdsk Dr1
CONDITIONS IOH = -12 mA IOL = 12 mA Measure between 0.8 V and 2.0 V Measure between 2.0 V and 0.8 V Stable VDD, valid clock on REF CL = 30 pF CL = 10 pF Measured at 1.4 V, Fout = 66.7 MHz Measured at VDD/2, Fout < 50.0 MHz Measured at 66.7 MHz, loaded outputs 10,000 cycles, CL = 30 pF 10,000 cycles, CL = 30 pF Measured at 1.4 V Measured at 1.4 V, within a group Measured at VDD/2,on CLKOUT pins Measured at 1.4 V
MIN 2.4
TYP
MAX 0.4 1.5 1.5 1 100 133 60 55 125 100 30 215 100 700 700
1.2 1.2 10 10 40 45 -100
50 50 70 14
UNITS V V ns ns mS MHz MHz % % ps ps ps ps ps ps ps
Notes: 1. Guaranteed by design and characterization, not 100% tested in production.
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ICS91309
Output to Output Skew
The skew between CLKOUT and the CLKA/B outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLKA/B outputs are less loaded than CLKOUT, CLKA/B outputs will lead it; and if the CLKA/B is more loaded than CLKOUT, CLKA/B will lag the CLKOUT. Since the CLKOUT and the CLKA/B outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds.
REF input and all outputs loaded Equally
REF input and CLKA/B outputs loaded equally, with CLKOUT loaded More.
REF input and CLKA/B outputs loaded equally, with CLKOUT loaded Less.
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Timing diagrams with different loading configurations
5
ICS91309
Application Suggestion:
ICS91309 is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise generated by charging or discharging of internal or external capacitor on the power supply pins. This type of noise will cause excess jitter to the outputs of ICS91309. Below is a recommended lay out to alleviate any addition noise. For additional information on FT. layout, please refer to our AN07. The 0.1 uF capacitors should be connected as close as possible to power pins (4 & 13). An Isolated power plane with a 2.2 uF capacitor to ground will enhance the power line stability.
33 33 33
33 33
1 REF 2 CLKA1 3 CLKA2 4 VDD
CLKOUT 16 CLKA4 15 CLKA3 14 VDD 13 GND 12 CLKB4 11 CLKB3 10 FS1 9
0.1F 33 33
5 GND 6 CLKB1 7 CLKB2 8 FS2
0.1F 33 33
10K GND VDD
10K GND VDD
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ICS91309
SYMBOL
In Millimeters COMMON DIMENSIONS MIN MAX 1.35 0.1 -- 0.20 1.75 0.25 1.50 0.30
In Inches COMMON DIMENSIONS MIN MAX .053 .0040 -- .008 .069 .010 .059 .012
A A1 A2 b c D E E1 e L N ZD
0.18 0.25 SEE VARIATIONS 5.80 3.80 6.20 4.00 0.635 BASIC 0.40 1.27 SEE VARIATIONS 0 8 SEE VARIATIONS
.007 .010 SEE VARIATIONS .228 .150 .244 .157
0.025 BASIC .016 .050 SEE VARIATIONS 0 8 SEE VARIATIONS
VARIATIONS N 16 D mm. MIN MAX 4.80 5.00 ZD
(Ref)
0.23
D (inch) MIN MAX .189 .197
JEDEC MO-137 DOC# 10-0032
ZD (Ref) .009
6/1/00 REV B
Ordering Information
ICS91309yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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ICS91309
SYMBOL
N
C
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 1.35 0.10 0.33 1.75 0.25 0.51 .0532 .0040 .013 .0688 .0098 .020
L
A A1 B C D E e
INDEX AREA
E
H
0.19 0.25 SEE VARIATIONS 3.80 4.0 1.27 BASIC 5.80 0.25 6.20 0.50
.0075 .0098 SEE VARIATIONS .1497 .1574 0.050 BASIC .2284 .010 .2440 .020
12 D
h x 45 A A1 SEATING PLANE .10 (.004)
H
h L N VARIATIONS N 16
0.40 1.27 SEE VARIATIONS 0 8
.016 .050 SEE VARIATIONS 0 8
e
B
D mm. MIN 9.80 MAX 10.00 MIN .3859
D (inch) MAX .3937
150 mil (Narrow Body) SOIC
Ordering Information
ICS91309yMLF-T
Example:
ICS XXXX y M LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type M - SOIC Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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ICS91309
N
c
L
INDEX AREA
E1
E
12 D
A2 A1
A
4.40 mm. Body, 0.65 mm. Pitch TSSOP (173 mil) (25.6 mil) In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 6.40 BASIC 0.252 BASIC E1 4.30 4.50 .169 .177 e 0.65 BASIC 0.0256 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 VARIATIONS N 16 D mm. MIN 4.90 MAX 5.10 MIN .193 D (inch) MAX .201
-Ce
b SEATING PLANE
aaa C
Reference Doc.: JEDEC Publication 95, MO-153 10-0035
Ordering Information
ICS91309yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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